This invention relates generally to path buffers in processors, and more particularly to providing data buffers partitioned from a cache array.
Large computer systems with many data paths interconnecting a large number of processors, I/O devices, and sliced memories and caches, require many data buffers to temporarily hold data in transit from one location in the system to another. Implementing this large number of data path buffers using separate discrete arrays placed individually on a chip floorplan increases densities for wiring, and typically implements a number of smaller memory arrays that are not as area or power efficient as larger arrays typically used for cache memory. System capabilities may be limited by the number of such buffers that can be placed in a design. Smaller systems with chip real estate constraints may also suffer similar limitations.
Currently, cache memory arrays ware utilized only for holding data associative with data from main memory in a corresponding congruence class within the cache, and identified by a cache directory, and managed by a cache replacement algorithm. Other temporary buffers needed for holding data being manipulated or transported between points were implemented as separate dedicated buffers located elsewhere on the chip. Placing such dedicated data buffers increases chip area, wiring complexity, and power utilization and may limit the number of data buffers that may be provided, increase the area and cost of the chip, or both.